Sr. Asic Design Engineer
Eliteteck (Silicon Valley/San Jose, California)

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The Sr. ASIC Design Engineer will be responsible for:

- Coordinate ASIC design project from netlist to working silicon.

- Perform full chip netlist simulation and timing verification.

- Work with IC layout engineers to complete ASIC design physical
implementation and verification

- Work with internal production team to resolve IC chip package and test
related issues

- Interface with customers to resolve any technical issues

- Manage ASIC projects schedule and ensure smooth communication with
customers



Required Experience

- M.S.E.E. with 6+ years, or B.S.E.E. with 8+ years of relevant ASIC
implementation experience

- Experienced with Cadence and Synopsys design tools and methodology

- Hands on working capability on ASIC Synthesis, verilog simulation and
timing verification.

- Good understanding on System-On-Chip (SOC) and deep sub-micro design
process

Please include a brief cover letter with your resume submission highlighting any relevant skills pertaining to this job to wayne@eliteteck.com
Also, please include the following information:

1. Current Salary
2. Expected Salary
3. Location (if relocation is applicable)
4. Available start date
5. Interviewing availability
6. Job search status: (active or beginning stages)
7. Pending offers (if you have any offers, please explain)
8. Visa Status

Contact for more information:
Wayne Burton
Eliteteck
wayne@eliteteck.com
Web: http://www.eliteteck.com