Asic Design Engineer
Executive Direction, Inc. (Silicon Valley/San Jose, California)

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Enterprise Solutions Development team is seeking an outstanding engineer to join their team and spear head the design and implementation of best-in-class solution for high-speed serial connectivity solutions like PCI Express Primarily and other High Speed Interconnects. The challenges will not stop there, as their efforts to build real-customer applications will include the definition, IP core design and verification, inter-op, drivers and applications.

Accountabilities:

-Deliver quality PCI Express design and protocol for Gen1, Gen2 and beyond.

-Design with Verilog, synthesis tools, simulation tools and FPGA EDA tools.

-Specify, design, and verify HDL IP modules for FPGA and ASIC.

-Partner with Marketing to specify and communicate future IP products and new product enhancements.

-Develop product rollout plans, create and generate resource charts, schedule timelines, etc.

-Work cross functionally with software, applications, and marketing teams.

-Key contributor in a fast paced team environment designing outstanding in industry results.

Qualifications:

-BS/MS Electrical Engineering, Computer Science, or Computer Engineering.

-5+ years experience in ASIC/FPGA design.

-Knowledge of system level debugging.

-Knowledge of serial I/O protocols (Serial RapidIO, HyperTransport) a plus.

-Scripting and programming languages experience such as: Perl, Tcl, Make, C, C++, System Verilog desired.

-Practical experience with PCI Express and Verilog or VHDL.

-Architecture, design and verification experience.

-Analytical with strong written and verbal communication skills.

Our client offers a wide range of memory interface and high-speed connectivity support in their FPGA device families. Their Intellectual Property (IP) and Solutions portfolio for these applications augment their device capabilities. While they have been successful in helping their customers slash down their time-to-market with their high performance and ready-to-use IP’s, they want to continue to invite experts to challenge the status quo!