Advanced Lithography Process Development Engineer
Spansion (Silicon Valley/San Jose, California)

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Position Description:

Purpose of this Group: The Advanced Process Technology group develops and transfers to production, all of Spansion’s NVM silicon process technology. Seamless collaboration with the Device/Integration, Yield/Reliability and sustaining Fab teams delivers leading edge silicon technology in support of Spansion’ product roadmap. This team of dedicated, energetic professionals, utilize the state of the art 300mm process equipment in the Submicron Development Center. They evaluate and select next generation tools, develop and characterize process recipes, and help integrate advanced Lithography, Etch, Thin Films, Diffusion, Ion Implant, CMP, and Copper interconnect modules, currently focused on the 32nm technology node. Job Description: Job duties will also include characterization and enabling of the available features and options offered by the tool supplier to utilize the full tool capability. Transfer of the knowledge to the Spansion’s manufacturing Fabs to improve lithographic process windows and insure high yields on products. This position requires working in highly dynamic and motivated team of lithography professionals.

To Apply Visit Spansion

Qualifications:

Education: Education: PhD or Master’s Degree in physics with excellent knowledge of optics is preferred. Min 5 years experience in a field of photolithography research and development. Experience: Knowledge of photolithography exposure tools, e.g. scanners, experience in evaluating exposure tools, benchmarking suppliers, working on JDP projects with the equipment suppliers, developing tool specifications based on lithographic simulations and experimental data to support Spansion’s GDR (geometric design rules) road map. Developing budgets for overlay requirements (including tool contribution) and focus budgets for the Flash technology nodes. Working with the layer process developers/engineers to insure optimum overlay performance (overlay target optimization by simulation and experiments) to minimize process induced overlay errors.